E-mail: jihoonkim[at]

Ji-Hoon Kim, Ph.D.

Associate Professor
Ewha Womans University

Educational Backgrounds

  • Mar.2004 ~ Aug. 2009

Ph.D. in Electrical Engineering,
KAIST, Daejeon, Korea

  • Mar.2000 ~ Feb. 2004

B.S. in Electrical Engineering,
KAIST, Daejeon, Korea

Professional Experiences

  • Mar.2018 ~ Present

Associate Professor,
Ewha Womans University, Seoul, Korea

  • Mar.2016 ~ Feb.2018

Associate Professor,
SeoulTech, Seoul, Korea

  • Mar.2015 ~ Feb.2016

Associate Professor,
Chungnam National University, Daejeon, Korea

  • Mar.2010 ~ Feb.2015

Assistant Professor,
Chungnam National University, Daejeon, Korea

  • July.2009 ~ Feb.2010

Senior Engineer,
DMC R&D Center,
Samsung Electronics, Suwon, Korea

Professional Activities

  • IEEE Senior Member
  • IDEC (IC Design Education Center) Steering Committee
  • JSTS (Journal of Semiconductor Technology and Science) Associate Editor
  • Technical Program Committee
    • IEEE Asian Solid-State Circuit Conference (A-SSCC)
    • Asia and South Pacific Design Automation Conference (ASP-DAC)
    • IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
    • IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
    • International SoC Design Conference (ISOCC)
    • Korean Conference on Semiconductor (KCS)

Invited Talks

  • [2019] “디지털 SoC 설계 관점에서의 차량용 반도체 고려사항 및 SEooC 설계 방법론,” Memory Division, Samsung Electronics
  • [2019] “보안프로세서 연구동향,” EDA Summer Workshop, IEEE CEDA Seoul Chapter
  • [2019] “보안프로세서 연구동향 및 RISC-V의 활용,” 보안 SoC 설계기술 워크샵, 대한전자공학회
  • [2019] “Application of Functional Safety & SEooC to Semiconductors,” Silicon Works
  • [2019] “On-Device AI기반 스마트 헬스케어 디바이스 개발 동향,” 이화메디테크포럼
  • [2018] “Challenges and Opportunities: From Digital VLSI to System Architecture,” Dept. of EE, KAIST
  • [2018] “SSVEP-based Headset-Type BCI for Paralyzed Patients,” 컴퓨터시스템소사이어티 동계워크샵, 한국정보과학회
  • [2017] “Introduction to RISC-V,” ETRI
  • [2017] “Introduction to RISC-V,” 국가보안기술연구소
  • [2016] “Let’s Talk about CPU Core,” Dept. of EE, POSTECH
  • [2016] “Secure Processor Trend,” Research IP Discovering, 한국반도체산업협회
  • [2016] “Arm Cortex-M3 with Security Consideration,” 국가보안기술연구소
  • [2015] “SoC Essentials for IoT Sensor Nodes,” RF/Analog 워크샵, 대한전자공학회
  • [2015] “Error Correction Codes for NAND Flash Memory,” SK Hynix
  • [2015] “Introduction to Core-A Processor,” ETRI
  • [2012] “Turbo Decoders for Wireless Communication Systems: Algorithm, Architecture, and Implementation,” 오류정정 알고리즘 및 아키텍쳐 기술 워크샵, 대한전자공학회
  • [2010] “Application-Specific System-on-Chip Design from the System Architect Point of View,” SAIT, Samsung Electronics
  • [2010] “Introduction to Core-A Processor: A Fully Synthesizable 32-bit Embedded Processor,” Dept. of EE, POSTECH